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| 1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2001-2005, zarlink semiconductor inc. all rights reserved. features ? compatible with: ? bellcore gr-30-core, sr-tsv-002476, ansi/tia/eia-716, tia/eia-777; ? etsi ets 300 778-1 (fsk only variant) & -2; ? bt (british telecom) sin227 & sin242 ? bellcore ?cpe alerting signal? (cas), etsi ?dual tone alerting signal? (dt-as), bt idle state and loop state ?tone alert signal? detection ? 1200 baud bell 202 and ccitt v.23 fsk demodulation ? separate differential input amplifiers with adjustable gain for tip/ring and telephone hybrid or speech ic connections ? selectable 3-wire fsk data interface (bit stream or 1 byte buffer) ? facility to monitor the stop bit for framing error check ? fsk carrier detect status output ? 3 to 5v +/- 10% supply voltage ? uses 3.579545 mhz crystal or ceramic resonator ? low power cmos with power down applications ? bellcore cid (calling identity delivery) and cidcw (calling identity delivery on call waiting) telephones and adjuncts ? etsi, bt clip (calling line identity presentation) and clip with call waiting telephones and adjuncts ? fax and answering machines ? computer telephony integration (cti) systems august 2005 ordering information mt88e45bn 20 pin ssop tubes MT88E45BS 20 pin soic tubes MT88E45BSr 20 pin soic tape & reel mt88ebnr 20 pin ssop tape & reel mt88e45bn1 20 pin ssop* tubes mt88e45bnr1 20 pin ssop* tape & reel *pb free matte tin -40 c to +85 c mt88e45 4-wire calling number identification circuit 2 (4-wire cnic2) data sheet figure 1 - functional block diagram anti-alias filter fsk bandpass fsk demodulator + - + - data timing recovery carrier detector 2130hz bandpass 2750hz bandpass tone detection algorithm fsken+tip/ring casen hybrid casen guard time mux dr std bias generator oscillator control bit decode fsken casen pwdn in1+ in1- gs1 in2+ in2- gs2 v ref osc1 osc2 cb0 cb2 cb1 data dclk cd dr /std st/gt est vdd vss mode mode fsken casen casen pwdn pwdn pwdn pwdn
mt88e45 data sheet 2 zarlink semiconductor inc. description the mt88e45b is a low power cmos integrated circuit suitable for receiving the physical layer signals used in north american (bellcore) calling identity delivery on call waiting (cidcw) and calling identity delivery (cid) services. it is also suitable for etsi and bt calling line identity presentation (clip) and clip with call waiting services. the mt88e45b contains a 1200 baud bell 202/ccitt v.23 fsk demodulator and a cas/dt-as detector. two input op-amps allow the mt88e45b to be connected to both tip/ring and the telephone hybrid or speech ic receive pair for optimal cidcw telephone architectural implementation. fsk demodulat ion is always on tip/ring, while cas detection can be on tip/ring or hybrid receive. tip/ring cas detection is required for the bellcore/tia multiple extension interworking (mei) and bt?s on-hook cl ip. a selectable fsk data interface allows the data to be processed as a bit stream or extracted from a 1 byte on chip buffer. power management has been incorporated to power down the fsk or cas section when not required. fu ll chip power down is also available. the mt88e45b is suitable for applications using a fixed power sour ce (with a +/-10% variation) between 3 and 5 v. mt88e45 data sheet 3 zarlink semiconductor inc. figure 2 - pin connections pin description pin # name description 1v ref voltage reference (output). nominally vdd/2. it is used to bias the tip/ring and hybrid input op- amps. 2in1+ tip/ring op-amp non-inverting (input). 3in1- tip/ring op-amp inverting (input). 4gs1 tip/ring gain select (output). this is the output of the tip/ring connection op-amp. the op- amp should be used to connect the mt88e45b to tip and ring. the tip/ring signal can be amplified or attenuated at gs1 via selection of the feedback resistor between gs1 and in1-. fsk demodulation (which is always on tip/ring) or cas detection (for mei or bt on-hook clip) of the gs1 signal is enabled via the cb1 and cb2 pins. see tables 1 and 2. 5 vss power supply ground. 6osc1 oscillator (input). crystal connection. this pin can also be driven directly from an external clock source. 7osc2 oscillator (output). crystal connection. when osc1 is driven by an external clock, this pin should be left open. 8cb0 control bit 0 (cmos input) . this pin is used primarily to select the 3-wire fsk data interface mode. when it is low, interface mode 0 is select ed where the fsk bit stream is output directly. when it is high, interface mode 1 is selected where the fsk byte is stored in a 1 byte buffer which can be read serially by the application?s microcontroller. the fsk interface is consisted of the data, dclk and dr /std pins. see the 3 pin descriptions to understand how cb0 affects the fsk interface. when cb0 is high and cb1, cb2 are both low the mt88e45b is put into a power down state consuming minimal power supply current. see tables 1 and 2. 9 dclk 3-wire fsk interface data clo ck (schmitt input/cmos output). in mode 0 (when the cb0 pin is logic low) this is a cmos output which deno tes the nominal mid-point of a fsk data bit. in mode 1 (when the cb0 pin is logic high) this is a schmitt trigger input used to shift the fsk data byte out to the data pin. 1 2 3 4 5 6 9 10 20 19 18 17 16 15 14 13 v ref in1+ in1- gs1 vss osc1 dclk data in2+ in2- gs2 cb2 cb1 vdd cd st/gt mt88e45b 7 osc2 8 cb0 12 11 est dr /std mt88e45 data sheet 4 zarlink semiconductor inc. 10 data 3-wire fsk interface data (cmos output). mark frequency corresponds to logical 1. space frequency corresponds to logical 0. in mode 0 (when the cb0 pin is logic low) the fsk serial bit stream is output to the data pin directly. in mode 1 (when the cb0 pin is logic high) the start bit is stripped off, the data byte and the trailing stop bit are stored in a 9 bit buffer. at the end of each word signalled by the dr /std pin, the microcontroller should shift the byte out onto the data pin by applying 8 read pulses to the dclk pin. a 9th dclk pulse will shift out t he stop bit for framing error checking. 11 dr /std 3-wire fsk interface data ready/cas detection delayed steering (cmos output). active low. when fsk demodulation is enabled via the cb1 and cb2 pins this pin is the data ready output. it denotes the end of a word. in both fsk interfac e modes 0 and 1, it is normally hi and goes low for half a bit time at the end of a word. but in mode 1 if dclk starts during dr low, the first rising edge of the dclk input will return dr to high. this feature allows an interrupt requested by a low going dr to be cleared upon reading the first data bit. when cas detection is enabled via the cb1 and cb2 pins this pin is the delayed steering output. it goes low to indicate that a time qualified cas has been detected. 12 est cas detection early steering (cmos output). active high. this pin is the raw cas detection output. it goes high to indicate the presence of a signal meet ing the cas accept frequencies and signal level. it is used in conjunction with the st/gt pin and external components to time qualify the detection to determine whether the signal is a real cas. 13 st/gt cas detection steering/guard time (cmos output/analog input). it is used in conjunction with the est pin and external components to ti me qualify the detection to determine whether the signal is a real cas. a voltage greater than v tgt at this pin causes the mt88e45b to indicate that a cas has been detected by asserting the dr /std pin low. a voltage less than v tgt frees up the mt88e45b to accept a new cas and returns dr /std to high. 14 cd carrier detect (cmos output). active low. a logic low indicates that an fsk signal is presen t. a time hysteresis is provided to allow for momentary signal discontinuity. the demodulated fsk data is ignored by the mt88e45b until carrier detect has been activated. 15 vdd positive power supply. 16 cb1 control bit 1 (cmos input). together with cb2 this pin sele cts the mt88e45b?s functionality between fsk demodulation, tip/ring ca s detection and hybrid cas detection. when cb0 is high and cb1, cb2 are both low the mt88e45b is put into a power down state consuming minimal power supply current. see tables 1 and 2. 17 cb2 control bit 2 (cmos input). together with cb1 this pin sele cts the mt88e45b?s functionality between fsk demodulation, tip/ring ca s detection and hybrid cas detection. when cb0 is high and cb1, cb2 are both low the mt88e45b is put into a power down state consuming minimal power supply current. see tables 1 and 2. 18 gs2 hybrid gain select (output). this is the output of the hybrid receive connection op-amp. the op- amp should be used to connect the mt88e45b to the telephone hybrid or speech ic receive pair. the hybrid receive signal can be amplified or attenuated at gs2 via selection of the feedback resistor between gs2 and in2-. when the cpe is off-hook cas detection of the gs2 signal should be enabled via the cb1 and cb2 pins. see tables 1 and 2. 19 in2- hybrid op-amp inverting (input). 20 in2+ hybrid op-amp non-inverting (input). pin description pin # name description mt88e45 data sheet 5 zarlink semiconductor inc. table 1 - cb0/1/2 functionality the number of control bits (cb) required to interface the mt88e45b with the microcontroller depends on the functionality of the application, as shown in table 2. table 2 - control bit functionality groups functional overview the mt88e45b is compatible with fsk and fsk plus cas (cpe alerting signal) based caller id services around the world. caller id is the generic name for a group of services offered by telephone operating companies whereby information about the calling party is de livered to the subscriber . in europe and some ot her countries caller id is known as calling line identity presentation (clip). etsi calls cas ?dual tone alerting signal? (dt-as), bt calls it ?tone alert signal?. depending on the service, data delivery can occur when th e line is in the on-hook or off-hook state. in most countries the data is modulated in eit her bell 202 or ccitt v.23 fsk format and transmitted at 1200 baud from the serving end office to the subscriber?s terminal. additionally in off-hook signalling, the special dual tone cas is used cb0 cb1 cb2 fsk interface function 0/1 1 1 set by cb0 fsk demodulation. tip/ring input (gs1) selected. dr /std is dr . 0/1 1 0 set by cb0 hybrid cas detection. hybrid receive input (gs2) selected. dr /std is std . 0/1 0 1 set by cb0 tip/ring cas detection. tip/ring input (gs1) selected. dr /std is std . when the line is off-hook, a bellcore/tia multiple extension interworking (mei) compatible type 2 cpe should be able to detect cas from tip/ring while the cpe is on-hook because it may be the ack sender. tip/ring cas detection is also required for bt?s on-hook clip. 1 0 0 mode 1 power down. the mt88e45b is disabled and draws virtually no power supply current. 0 0 0 mode 0 reserved for factory testing. functionality group controls description fsk (mode 0 or 1) and hybrid cas only (non mei compatible) cb2 cb0 is hardwired to vdd or vss to select the fsk interface. cb1 hardwired to vdd. the microcontroller uses cb2 to select between the 2 functions. fsk (mode 0 or 1), hybrid cas, tip/ring cas (mei compatible or bt on-hook clip) cb1 cb2 cb0 is hardwired to vdd or vss to select the fsk interface. the microcontroller uses cb1 and cb2 to select between the 3 functions. fsk (mode 1), hybrid cas, tip/ring cas, power down (mei compatible or bt on-hook clip) cb1 cb2 cb0 is hardwired to vdd to select fsk interface mode 1. the microcontroller uses cb1 and cb2 to select between the 4 functions. fsk (mode 0), hybrid cas, tip/ring cas, power down (mei compatible or bt on-hook clip) cb0 cb1 cb2 all 3 pins are required. mt88e45 data sheet 6 zarlink semiconductor inc. to alert the terminal before fsk data transmission. bt uses cas to alert th e terminal prior to fsk in both on-hook (idle state) and off-hook (loop state) signalling. in north america, caller id uses the voiceband data tran smission interface defined in the bellcore document gr- 30-core. the terminal or cpe (customer premises e quipment) requirements are defined in bellcore document sr-tsv-002476. typical serv ices are cnd (calling numb er delivery), cnam (ca lling name delivery), vmwi (visual message waiting indica tor) and cidcw (calling identi ty delivery on call waiting). in europe, caller id requirements are defined by etsi . the cpe documents are ets 300 778-1 for on-hook, ets 300 778-2 for off-hook. the end office requirements ar e ets 300 659-1 (on-hook) and ets 300 659-2 (off-hook). etsi has defined services such as clip and clip with call waiting which are similar to those of bellcore. some european countries produce their own natio nal specifications. for example, in the uk bt?s standards are sin227 and sin242, the uk cca (cable communicati ons association) stan dard is tw/p&e/312. in on-hook caller id, such as cnd, cnam and clip, the info rmation is typically transmi tted (in fsk) from the end office before the subscriber picks up the phone. there are various methods such as between the first and second rings (north america), between an abbreviated ring and the first true ring (japan, france and germany). on-hook caller id can also occur without ringing for services such as vmwi. in bt?s on-hook clip, the signalling begins with a line polarity reversal, followed by cas and then fsk. bellcore calls an on-hook capable caller id cpe a ?type 1 cpe?. in off-hook caller id, such as cidcw and clip with call waiting, information about a new calling party is sent to the subscriber who is already engaged in a call. bellcor e?s method uses cas to alert the cpe. when the cpe detects cas and there are no off-hook extensions, the cpe should mute its transmission path and send an acknowledgment to the end office via a dtmf digit called ack. upon receiving ack, the end office will send the fsk data. bellcore calls an off-hook capable cpe a ?type 2 cpe?. a type 2 cpe is capable of off-hook and type 1 functionalities and should ack with a dtmf ?d?. the etsi and bt off-hook signalling protocols are similar to bellcore?s but with timing and signal parametric differ ences. etsi has no requirement for off-hook extension checking before ack. one factor affecting the quality of the cidcw service is the cpe?s cas speech immunity. although the end office has muted the far end party before and after it sends cas, the near end (the end which is to receive the information) user may be still talking. therefore the cpe must be able to detect cas successfully in the presence of near end speech. this is called the talkdown immunity . the cpe must also be immune to imitation of cas by speech from both ends of the connection because the c as detector is continuously exposed to speech throughout the call. this is called the talkoff immunity. if the cpe is a telephone, one way to achieve good cas s peech immunity is to put cas detection on the telephone hybrid or speech ic receive pair instead of on tip and ring. talkdown immunity im proves because the near end speech has been attenuated while the cas level is the same as on tip/ring, resulting in improved signal to speech ratio. talkoff immunity is also improved because the near end speech has been attenuated. in the bellcore sr-tsv-002476 issue 1 off-hook protocol , the cpe should not ack if it detected an off-hook extension. the fsk will not be sent and the customer will not receive the call waiting id. bellcore, together with the tia (telecommunication s industry association) tr41 .3.1 working group, has defined a cpe capability called multiple extension interworking (mei) which overcomes this problem. in the mei scheme, all mei compatible cpes must be capable of detecting cas when the line is off-hook, even though the cpe itself may be on-hook. this is because under some conditions an on-hook cpe may become the ack sender. another reason for the on-hook cpe to detect cas is to maintain synchronous call logs between on and off-hook cpes. when cas is received and all off-hook cpes are mei compatible, one of the cpes will ack and all compatible cpes will receive fsk. a problem arises in a cpe where the cas detector is c onnected only to the hybrid or speech ic receive pair: it cannot detect cas when it is on-hook. the reason is that when the cpe is on-hook either the hybrid/speech ic is non functional or the signal level is severely attenu ated. therefore an on-hook ty pe 2 cpe must be capable of mt88e45 data sheet 7 zarlink semiconductor inc. detecting cas from tip/ring, in addition to detecting cas from the hybrid/speech ic receive signal when it is off- hook. the mt88e45b offers an optimal solution which combines good speech immunity and mei compatibility. two input op-amps allow the mt88e45b to be connected both to tip/ring and to the hybrid/speech ic receive pair. both connections can be differential or singl e ended. fsk demodulation is always on the tip/ring si gnal. cas detection can be from the tip/ring or hybrid/speech ic receive si gnal. being able to detect cas on tip/ring also makes the mt88e45b suitable for bt on-hook clip applications. for applications such as those in most european coun tries where tip/ring cas detection is not needed, then the tip/ring and hybrid op-amp gains can be tailored independently to meet country specific fsk and cas signal level requirements respectively. note that since the hybrid op-amp is for cas detection only, its gain can always be tailored specifically for the cas signal level. the fsk demodulator is compatible with bellcore, et si and bt standards. the demodulated fsk data is either output directly (bit stream mode) or stored in a one byte buffer (buffer mode). in the buffer mode, the stop bit immediately following a byte is also stored and can be shifted out after the data byte. this facility allows for framing error checking required in type 2 cpes. in the bit stream mode, two timing signals are provided. one indicates the bit sampling instants of the data byte, the other the end of byte. a carrier detector indicates presence of signal and shuts off the data stream when there is no signal. the entire chip can be put into a virtually zero curr ent power down mode. the inpu t op-amps, fsk demodulator, cas detector and the oscillator are all shut off. furthermore, power management has been incorporated to minimize operating current. when fsk is selected the cas detector is powered down. when cas is selected the fsk demodulator is powered down. functional description 3 to 5 v operation the mt88e45b?s fsk and cas reject levels are proporti onal to vdd. when operated at vdd equal 3 v +/- 10%, to keep the fsk and cas reject levels as at 5 v (nominal ) the tip/ring and hybrid op-amp gains should be reduced from those of 5 v. gains for nominal vdd (with a +/- 10% variation) other than 3 or 5 v can be chosen as interpolation between the 3 and 5 v settings. input configuration the mt88e45b provides an input arrangement comprised of two op-amps and a bias source (v ref ). v ref is a low impedance voltage source which is used to bias the op-amp inputs at vdd/2. the tip/ri ng op-amp (in1+, in1-, gs1 pins) is for connecting to tip and ring. the hybrid op-amp (in2+, in2-, gs2 pins) is for connecting to the telephone hybrid or speech ic receive pair. either fsk or cas detection can be selected for the tip/ ring connection, while the hybrid connection is for cas detection only. phrased in another way, fsk demodulation is always on tip/ring, while cas detection can be on tip/ring or hybrid receive. tip/ring cas detection is required for mei and bt on-hook clip, while hybrid cas detection is needed for optimal cas speech immunity. the feedback resistor connected between gs1 and in1- can be used to adjust the tip/ring signal gain. the feedback resistor connected between gs2 and in2- can be used to adjust the hy brid receive signal gain. when the tip/ring op-amp is selected, the gs2 signal is ignored. when the hybrid op-amp is selected, the gs1 signal is ignored. either or both op-amps can be configured in the single ended input config uration shown in figure 33, or in the differential input config uration shown in figure 44. mt88e45 data sheet 8 zarlink semiconductor inc. figure 3 - single ended input configuration figure 4 - differential input configuration cas detection in north america, cas is used in off-hook signalling only. in europe (etsi) it is used in off-hoo k signalling, and by bt in both on and off-hook signalling. etsi calls it t he dual tone alerting signal (d t-as). although the etsi on- hook standard contains a dt-as specification, bt is the only administration known to employ cas in on-hook signalling. (bt calls it tone aler t signal.) the cas/dt-as characteri stics are summarized in table 3. 2130 hz and 2750 hz cas/dt-as characteristics bellcore a (off-hook only) etsi b (off-hook) bt c (off-hook = ?loop state?) (on-hook = ?idle state?) frequency tolerance +/-0.5% +/-0.5% off-hook: +/-0.6% on-hook: +/-1.1% signal level (per tone) -14 to -32 dbm d -9.78 to -32.78 dbm (-12 to -35 dbv e ) +0.22 to -37.78 dbm (-2 to -40 dbv) reject level (per tone) -4 5 dbm on-hook: -43.78 dbm (-46 dbv) maximum twist (v 2130hz /v 2750hz ) +/-6 db +/-6 db +/-7 db c r in in+ in- gs highpass corner frequency f -3db = 1/(2 r in c) r f voltage gain (a v ) = r f / r in v ref c1 r1 c2 r4 r3 r2 r5 in+ in- gs v ref differential input amplifier c1 = c2 r1 = r4 (for unity gain r5= r4) r3 = (r2r5) / (r2 + r5) voltage gain (a v diff) = r5/r1 input impedance (z in diff) = 2 r1 2 + (1/ c) 2 highpass corner frequency f -3db = 1/(2 r1c1) mt88e45 data sheet 9 zarlink semiconductor inc. table 3 - cas/dt-as characteristics table 3 shows the hybrid op-amp (gs2) gain for operation at 3 v and 5 v nominal vdd, with a 10% vdd variation. for 3 v operation, the hybrid op-amp gain should be reduc ed from the 5 v setting to ma intain the cas reject level and to maintain the talkoff immunity: the cas threshold is directly proportional to vdd, when vdd is reduced the threshold becomes lower, hence lower level cas are accept ed. if the gain is not redu ced, the mt88e45b will be more talkoff prone. in table 3, the gs2 gain is shown as a range. by adopting the lower gain, talkoff immunity can be improved. when cas detection is selected, the dual purpose output pin dr /std is std . std goes low when cas has been detected, and returns high after cas has ended. cas guard time the guard time circuit shown in figure 55 implements a timing algorithm which determi nes whether the signal is a cas. proper selection of the guard time(s) is key to good s peech immunity. the first indication that there might be a cas is when est goes high. est high indi cates that both tones ar e present. est low indicates that one or both tones is not present. std low indicates that cas has been detected. when std returns high it indicates that cas has ended. the timing algorithm consists of 2 components: a tone present guard time (t gp ) and a tone absent guard time (t ga ). t gp sets the minimum accept duration for cas. that is, both tones must be detected continuously for t gp for std to go low to indicate that cas has been detected. for std to return high to indicate that cas has ended, one or both tones must have disappeared for t ga . the purpose of t ga is to bridge over momentary est dropouts once est has met the minimum tone duration so as to decrease the likelihood of a long ta lkoff being broken up into several talkoffs. usually t ga is set very short or removed altogether becaus e there is another way to deal with the problem (by ignoring further detections for 2 seconds after every detection). duration 75 to 85 ms 75 to 85 ms off-hook: 80 to 85 ms on-hook: 88 to 110 ms reject duration off-hook: <=70 ms on-hook: <=20 ms signal to noise ratio speech speech off-hook: speech on-hook: >= 20 db (300-3400 hz) hybrid op-amp (gs2) gain vdd = 5v +/- 10% 0 to -5 db 0 to -5 db 0 db hybrid op-amp (gs2) gain vdd = 3v +/- 10% -3.5 to -8.5 db -3.5 to -8.5 db -3.5 db a. sr-tsv-002476, issue 1 dec 1992 b. ets 300 778-2 jan 98. the dt -as plus fsk variant of etsi on-hook signalling descr ibed in ets 300 778- 1 is not supported because on-hook dt-as uses the gs1 op-amp. with the gs1 gain in table 4, the dt-as minimum level will be below the mt88e45b?s minimum accept level. c. sin227 issue 3 nov 97, sin242 issue 2 nov 96 d. dbm - decibels above or below a reference power of 1 mw into 600 ohms. 0 dbm = 0.7746 vrms. e. dbv - decibels above or below a reference voltage of 1 vrms. 0 dbv = 1 vrms 2130 hz and 2750 hz cas/dt-as characteristics bellcore a (off-hook only) etsi b (off-hook) bt c (off-hook = ?loop state?) (on-hook = ?idle state?) mt88e45 data sheet 10 zarlink semiconductor inc. figure 5 - cas guard time circuit operation tone present guard time (t gp ) operation: in figure 5 5 initially there is no cas, est is low so q1 is off. c has been fully charged applying 0 v to st/gt so q2 is on. when both tones are detected est goes high and turns off q2. because c has been fully charged (st/gt=0v), the comparator output is low and q1 stays off. with both q1 and q2 off the high at est discharges c through r1 and the st/gt voltage increases from 0 v. when the voltage exceeds the comparator threshold vtgt, which is typicall y 0.5 vdd, the comparator out put goes high; q1 turns on and accelerates the discharge of c (st/gt goes quickly to vdd); std goes low to indicate that a valid cas has been received. if one or bot h tones disappeared before t gp has been reached (i.e. when st/gt voltage is still below vtgt), q2 turns back on and charges c quickly to bring the st/gt voltage back to 0 v. then if est goes high again the t gp duration must start over. tone absent guard time (t ga ) operation: in figure 5 5 initiall y both tones have been detected for t gp so c is fully discharged and st/gt is at vdd. whil e both tones continue to be detected est stays high; st/gt is at vdd (the comparator output is high); so q1 is on and q2 is off. when one or both tones stop est goes low and turns off q1. because c is fully discharged (st/gt=vdd), the comparator output is high and q2 stays off. with both q1 and q2 off the low at est charges c through rp=(r1 || r2) a nd the st/gt voltage falls towards 0v. when the voltage has fallen below vtgt, the comparator out put goes low. since est is also low q2 turns on and accelerates the charging of c so that st/gt goes quickly to 0v. std goes high to indicate that the cas has ended. if est goes back to high before t ga has been reached (i.e. when st/gt voltage is still above v tgt ), q1 turns back on and discharges c quickly to bring the st/gt voltage back to vdd. then if est goes low again the t ga duration must start over. to set t ga =0, set r2 to 0. + - vtgt est st/gt vdd dr / std = vss both tones present c q1 q2 mt88e45b comparator p n cas est st/gt std t dp t da t ga t gp r1 r2 rp=r1 || r2 t abs t rec indicates std in cas detection mode t gp =r1c ln [vdd / (vdd-vtgt)] t ga =rpc ln vdd - vdiode (rp/r2) vtgt - vdiode (rp/r2) rp=r1 || r2 t ga =0 if r2=0 v diode mt88e45 data sheet 11 zarlink semiconductor inc. in figure 55, t dp is the delay from the start of cas to est responding, t da is the delay from the end of cas to est responding. the total delay from the start of cas to std responding is t rec =t dp +t gp. the total delay from the end of cas to std responding is t abs =t da +t ga . table 4 - fsk signal characteristics fsk demodulation the fsk characteristics are shown in table 4. in nort h america, tia (telecommunications industry association) also sets standards. the type 1 caller id cpe standard is ansi/tia/eia-716. the type 2 standard is tia/eia-777. the north american fsk characteristics in table 4 are from ansi/tia/eia-716. they differ from those bellcore published in sr-tsv-002476 and sr-3004. bellcore is r epresented in tr41.3.1 and will synchronize to the tia requirements in its future documents. the tia type 1 standard includes an fsk reject level: ? if data is not preceded by ringing (e.g., vmwi), fsk signals below 3mvrms (-48.24 dbm) shall be rejected ? if data is preceded by ringing, fsk detection may be extended below 3mvrms the mt88e45b is compliant with the bellcore/tia, etsi an d bt requirements with the tip/ring op-amp gains in table 4. in europe if the country specific fsk requirem ents do not incorporate etsi?s fsk reject level then the tip/ring op-amp gain can also be 0 db at 5 v and -3.5 db at 3 v to meet the etsi minimum cas level for on-hook signalling (-40 dbv). parameter north america: bellcore a europe: etsi b uk: bt c mark (logical 1) frequency 1200 hz +/- 1% 1300 hz +/- 1.5% space (logical 0) frequency 2200 hz +/- 1% 2100 hz +/- 1.5% received signal level -4.23 to -36.20 dbm (476 to 12 mvrms) d -5.78 to -33.78 dbm e (-8 to -36 dbv) f,g -5.78 to -37.78 dbm (-8 to -40 dbv) signal reject level -48.24 dbm (3mvrms) for on-hook no ring signalling such as vmwi on-hook only: -47.78 dbm (-50dbv) transmission rate 1200 baud +/- 1% 1200 baud +/- 1% twist (v mark /v space ) -6 to +10 db -6 to +6 db signal to noise ratio single tone (f): -18 db (f<=60hz) -12 db (60 mt88e45 data sheet 12 zarlink semiconductor inc. for 3 v operation, the fsk receiver becomes more sensitive and lower level signals will be accepted than at 5 v. to maintain the fsk reject level, the tip/ring input op-amp gain should be reduced. note t hat since the tip/ring op- amp is also used for tip/ring cas det ection, the cas level will also be reduced for on-hook detection. fsk data interface the mt88e45b provides a powerful dual mode 3-wire interface so that the data bytes in the demodulated fsk bit stream can be extracted without the need either for an exte rnal uart or for the cpe?s microcontroller to perform the function in software. the interface is specifically designed for the 1200 baud rate and is consisted of 3 pins: data, dclk (data clock) and dr (data ready). dr /std is a dual purpose output pin. when fsk is selected it is dr . two modes (modes 0 and 1) are selectable via the cb0 pin. in mode 0, the fsk bit stream is output directly. in mode 1, the data byte and the trailing st op bit are stored in a 9 bit buffer. if mode 1 is desired, the cb0 pin can be hardwired to vdd. if mode 0 is desired and full chip pow er down is not required, th e cb0 pin can be hardwired to vss. in bellcore?s off-hook protocol, a type 2 cpe should restor e the voicepath within 50 ms after the end of the fsk signal. due to noise, end of carrier detection is not always reliable. the tia type 2 standard stipulates that the cpe must detect the end of fsk when any one of the following occurs: ? absence of carrier signal or, ? more than five framing errors (trailing stop bit a 0 in stead of a 1) have been detected in the fsk message or, ? more than 150 ms of continuous mark signal or space signal has been detected. mode 0 - bit stream mode this mode is selected when the cb0 pin is low. in this m ode the fsk data is output directly to the data pin. dclk and dr pins are timing signal outputs (see figure 13. for each received stop and start bit sequence, the mt88e45 b outputs a fixed frequency cl ock string of 8 pulses at the dclk pin. each dclk rising edge o ccurs in the middle of a data bit ce ll. dclk is not generated for the start and stop bits. consequently, dclk will clock only valid data into a peripheral device such as a serial to parallel shift register or a microcontroller. t he mt88e45b also outputs an end of word pulse (data ready) at the dr pin. dr goes low for half a nominal bit time at the beginning of the trailing stop bit. it can be used to interrupt a microcontroller or cause a serial to parallel converter to pa rallel load its data into the microcontroller. since the dr rising edge occurs in the middle of the stop bit, it can al so be used to read the stop bit to check for framing error. alternatively, dclk and data may occupy 2 bits of a mi crocontroller?s input port. the microcontroller polls the input port and saves the data bit whenever dclk changes from low to high. when dr goes low, the word may then be assembled from the last 8 saved bits. data may also be connected to a personal computer?s seri al communication port after conversion from cmos to rs-232 voltage levels. mode 1 - buffer mode this mode is selected when the cb0 pin is high. in this mode the received byte is stored on chip. at the end of a byte dr goes low to indicate that a new byte has become available. the microcontroll er applies dclk pulses to read the register contents serially out of the data pin (see figure 1414). internal to the mt88e45b, the start bit is stripped off, the data bits and the trailing st op bit are sampled and stored. midway through the stop bit, the 8 data bits and the st op bit are parallel loaded into a 9 bit shift register and dr goes low. the register?s contents are shifted out to the data pin on the supplied dclk?s rising edges in the order they were received. the last bit must be shifte d out and dclk returned to low before the next dr . dclk must be low for t dds before dr goes low and must remain low for t ddh after dr has gone low (see figure 14). mt88e45 data sheet 13 zarlink semiconductor inc. if dclk begins while dr is low, dr will return to high upon the first dclk rising edge. if dr interrupts a microcontroller then this feature al lows the interrupt to be cleared by the first read pulse. otherwise dr is low for half a nominal bit time (1/2400 sec). reading the stop bit allows the software to check for framing errors. when framing error is not checked the microcontroller only needs to send 8 dclk pulses to shift the data byte out. carrier detect the carrier detector provides an indica tion of the presence of a signal in the fsk frequency band. it detects the presence of a signal of sufficient ampl itude at the output of the fsk bandpass filter. the signal is qualified by a frequency aware digital algorithm before the cd output is set low to indicate carr ier detection. a 10 ms hysteresis is provided to allow for momentary signal dropout once cd has been activated. cd is released when there is no activity at the fsk bandpa ss filter output for 10 ms. when cd is inactive (high), the raw output of the fsk demodul ator is ignored by the internal data timing recovery circuit. in mode 0 the data, dclk and dr pins are forced high. in mode 1 th e output shift regist er is not updated and dr is high; if dclk is cl ocked, data is undefined. note that signals such as speech, cas and dtmf tones also lie in the fsk frequency band and the carrier detector may be activated by these signals. th ey will be demodulated and presented as data. to avoid the false data, the mt88e45b should be put into cas or power down m ode when fsk is not expected. ringing, on the other hand, does not pose a problem as it is ignored by the carrier detector. interrupt the dr /std output can be used to interrupt a microcontroller . when the mt88e45b is the only interrupt source, dr /std can be connected directly to the microcontroller ?s interrupt input. figure 9 shows the necessary connections when the mt88e45b is one of many interrupt sources. the diodes and resistors implement a wired-or so that the microcontroller is interrupted (int low active or falling edge tri ggered) when one or more of int1 , int2 or dr /std is low. the microcontroller can determine which one of dr /std , int1 or int2 caused the interrupt by reading them into an input port. when system power is first applied and cb0/1/2 have al ready been configured to select cas detection, dr /std will power up as logic low. this is because there is no charge across the st/gt capa citor in fi gure 55, hence st/gt is at vdd which causes std to be low. if dr /std is used to interrupt a microc ontroller the interrupt will not clear until the capacitor has charged up. therefore upon in itial power up the microcon troller should ignore this interrupt source until there is sufficient time to charge the capacitor. alternatively, the mt88e45b can be put into power down mode: dr /std goes high and clears the interrupt, st/gt goes low and the capacitor will charge up quickly. power down the mt88e45b can be powered down to consume virtually no power supply current via a state of the cb0/1/2 pins. momentary transition of cb0/1/ 2 into the power down code will not activate power down. in power down mode both input op-amps, v ref and the oscillator are non functional. dclk becomes an input because to select the power down state cb0 is 1 which will select fsk interface mode 1. if the application uses fsk interface mode 0 and the mt88e45b needs to be powered down then a pull down resistor should be added at the dclk pin to define its state during power down (r15 in figure 7). when the mt88e45b is powered down data, dr /std , cd are high; est and st/gt are low. to reduce the operating current an intelligent power do wn feature has been incorpor ated. when fsk is selected, the cas detector is powered down. when cas is selected the fsk demodulator is powered down. the two input op-amps are not affected and bo th will remain operational. mt88e45 data sheet 14 zarlink semiconductor inc. oscillator the mt88e45b requires a 3.579545 mhz crystal or ceramic resonator to generate its oscillator clock. to meet the cas detection frequency tolerance specifications the crys tal or resonator must have a 0.1% frequency tolerance. the crystal specification is as follows: (e.g., cts mp036s) frequency: 3.579545 mhz frequency tolerance: 0.1% (over temperature range of the application) resonance mode: parallel load capacitance: 18 pf maximum series resistance: 150 ? maximum drive level: 2 mw alternatively an external cl ock source can be used. in which case the osc1 pin should be driven directly from a cmos buffer and the osc2 pin left open. for 5v+/-10% applications any number of mt88e45b?s can be connected as shown in figure 6 6 so that only one crystal is required. figure 6 - common crystal connection osc1 osc2 osc1 osc2 osc1 osc2 3.579545 mhz mt88e45b mt88e45b mt88e45b to the next mt88e45b (for 5v+/-10% applications only) mt88e45 data sheet 15 zarlink semiconductor inc. application circuits figure 7 - application circuit: bellc ore mei compatible type 2 telephone v ref in1+ in1- gs1 vss osc1 dclk data in2+ in2- gs2 cb2 cb1 vdd cd st/gt mt88e45b osc2 cb0 est dr /std telephone tx+ tx- rx+ rx- tip ring microphone speaker tip ring r1 r2 r3 r4 r5 r6 d1 d2 d3 d4 r7 r8 r9 r10 r11 r12 r13 r14 d5 c1 c2 c3 c4 xtal r15 c5 c6 hybrid or (fsk interface mode 1 selected) r15 is required only if both fsk interface mode 0 and power down features are used. c6 should be connected directly across vdd and vss pins unless stated otherwise, resistors are 1%, 0.1watt; capacitors are 5%, 6.3v. for 1000vrms, 60hz isolation from tip to earth and ring to earth: r1,r2 430k, 0.5w, 5%, 475v min. c1,c2 2n2, 1332v min. (e.g. irc type gs-3) if the 1000vrms is handled by other methods then this circuit has to meet the fcc part 68 type b ringer requirements: r1,r2 432k, 0.1w, 1%, 56v min. c1,c2 2n2, 212v min. common to both sets of r1,r2: 5v, 0db gain 3v, -3.5db gain r3,r4 34k c3,c4 2n2 r5,r10 53k6 35k7 r8,r9 464k c5 100n r6,r11 60k4 40k2 r13 825k c6 100n, 20% r7,r12 464k 309k r14 226k or 26k1 d1-d4 diodes. 1n4148 or equivalent r15 100k, 20% d5 diode. 1n4148 or equivalent xtal 3.579545mhz, 0.1% crystal or ceramic resonator vdd = to microcontroller = from microcontroller vss speech ic (symbolic) mt88e45 data sheet 16 zarlink semiconductor inc. figure 8 - gain ratio as a function of nominal vdd gain setting resistor calculation example for figure 8: ? for the desired nominal vdd, use figure 8 to determine approximate a v . ? for the gs1 op-amp, start with the 0 d b gain setting resistor values of r5 0db , r6 0db and r7 0db . in figure 7 these values are 53k7, 60k4 and 464 k respectively. keep c1,c2,r1,r2,r3,r4 as in figure 7 to maintain the highpass corner frequency constant for all gain settings. ? for the desired gain setting of a v : r7 av = r7 0db x a v scaled for desired gain. choose the closest standard resistor value as r7 av . actual a v from now on is r7 av /r7 0db r5 av = r5 0db x a v scaled for good common mode range. choose the closest standard resistor value as r5 av . 1/r6 av = 1/r5 av - 1/r7 av calculate r6 av so that r5 av =r6 av || r7 av . choose the closest standard resistor value as r6 av . ? repeat for r 10 , r 11 , r 12 for the gs2 op-amp. 3.0 3.5 4.0 4.5 5.0 nominal vdd (volts) 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 gain ratio 0.668 0.531 0.794 gain ratio for bellcore gs1, gs2 etsi gs2 op amps gain ratio for etsi gs1 op amp mt88e45 data sheet 17 zarlink semiconductor inc. example: ? for a gain of -3.5 db, a v =10 -3.5/20 = 0.668 ?r7 -3.5db = 464 k x 0.668 = 309k9, the closest standard resistor value is 309 k. a v is now 309 k/464 k = 0.666 ?r5 -3.5db = 53k6 x 0.666 = 35k7, the closest standard resistor value is 35k7. therefore r6 -3.5db is calculated to be 40k4, the closest standard resistor value is 40k2. figure 9 - application circuit: multiple interrupt source interrupt source 1 int1 (open drain) interrupt source 2 int2 (cmos) mt88e45b vdd resistor (r1) vdd resistor (r2) dr /std (cmos) int (input) microcontroller input port bit r1 can be opened and d1 shorted if the microcontroller does not read the int1 pin. d1 mt88e45 data sheet 18 zarlink semiconductor inc. * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ** under normal operating conditions voltage on any pin except supplies can be minimum v ss -1v to maximum v dd +1v for an input current limited to less than 200 ? ? typical figures are at 25 o c and are for design aid only: not guaranteed and not subject to production testing. absolute maximum ratings* - voltages are with respect to v ss unless otherwise stated parameter symbol min. max. units 1 supply voltage with respect to v ss v dd -0.3 6 v 2 voltage on any pin other than supplies ** v pin v ss -0.3 v dd +0.3 v 3 current at any pin other than supplies i pin 10 ma 4 storage temperature t st -65 150 o c recommended operating conditions - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym. min. typ. ? max. units 1 power supplies v dd 2.7 5.5 v 2 clock frequency f osc 3.579545 mhz 3 tolerance on clock frequency ? f osc -0.1 +0.1 % 4 operating temperature t op -40 85 o c dc electrical characteristics ? characteristics sym. min. typ. ? max. units test conditions 1 s u p p l y standby supply current i ddq 0.1 15 a all inputs are v dd /v ss except for oscillator pins. no analog input. outputs unloaded. cb0/1/2 = 1/0/0 2 operating supply current v dd = 5v 10% v dd = 3v 10% i dd 2.8 1.5 8 4.5 ma ma all inputs are v dd /v ss except for oscillator pins. no analog input. outputs unloaded. 3 power consumption po 44 mw 4 dclk schmitt input high threshold v t+ 0.44*v dd 0.64*v dd v schmitt input low threshold v t- 0.27*v dd 0.47*v dd v 5 schmitt hysteresis v hys 0.2 v 6 cb0 cb1 cb2 cmos input high voltage v ih 0.7*v dd v dd v cmos input low voltage v il v ss 0.3*v dd v 7 dclk data dr /std cd , est st/gt output high source current i oh 0.8 ma v oh =0.9*v dd mt88e45 data sheet 19 zarlink semiconductor inc. ? dc electrical characteristics are over recommended operating conditions, unless otherwise stated. ? typical figures are at 25 o c and are for design aid only: not guaranteed and not subject to production testing. ? ac electrical characteristics are over recommended operating conditions, unless otherwise stated. ? typical figures are at 25 o c and are for design aid only: not guaranteed and not subject to production testing *notes: 1. tip/ring signal level. input op-amp configured to 0db gain at vdd=5v+/-10%, -3.5db at vdd=3v+/-10%. 2. tip/ring signal level. input op-amp configured to 0db gain at vdd=5v+/-10%. 3. both tones have the same amplitude. 4. band limited random noise 300-3400hz. measurement valid only when tone is present. 5. dbv - decibels above or below a reference voltage of 1 vrms. 0 dbv = 1 vrms. signal level is per tone. 6. dbm - decibels above or below a reference power of 1 mw into 600 ohms. 0 dbm = 0.7746 vrms. signal level is per tone. 8 dclk data dr /std cd , est st/gt output low sink current i ol 2mav ol =0.1*v dd 9 in1+ in1- in2+ in2- input current iin1 1 av in =v dd to v ss dclk cb0 cb1 cb2 iin2 10 av in =v dd to v ss 1 0 st/gt output high- impedance current ioz1 5 av out =v dd to v ss 11 v ref output voltage v ref 0.5v dd -0.1 0.5v dd +0.1 v no load 1 2 output resistance r ref 2k ? 1 3 st/gt comparator threshold voltage v tgt 0.5v dd - 0.05 0.5v dd +0.05 v ac electrical characteristics ? - cas detection characteristic sym. min. typ. ? max. unit notes* 1 lower tone frequency f l 2130 hz 2 upper tone frequency f h 2750 hz 3 frequency deviation: accept 1.1% range within which tones are accepted 4 frequency deviation: reject 3.5% range outside of which tones are rejected 5 accept signal level (per tone) -40 -37.78 -2 0.22 dbv dbm 1, 5, 6 6 reject signal level (per tone) vdd=5v +/-10% only -46 -43.78 dbv dbm 2, 5, 6 7 reject signal level (per tone) vdd=3v+/-10% or 5v+/-10% -47.22 -45 dbv dbm 1, 5, 6 8 twist: 20 log (v 2130hz /v 2750hz )-7+7db 9 signal to noise ratio snr cas 20 db 3,4 dc electrical characteristics ? (continued) characteristics sym. min. typ. ? max. units test conditions mt88e45 data sheet 20 zarlink semiconductor inc. ? ac electrical characteristics are over recommended operating conditions, unless otherwise stated. ? typical figures are nominal values and are for design aid only: not guaranteed and not subject to production testing. *notes: 1. both mark and space have the same amplitude. 2. tip/ring signal level. input op-amp configured to 0db gain at vdd=5v+/-10%, -3.5db at vdd=3v+/-10%. 3. band limited random noise (200-3400hz). present when fsk signal is present. note that the bt band is 300-3400hz, the bellcore band is 0-4khz. 4. dbv - decibels above or below a reference voltage of 1 vrms. 0 dbv = 1 vrms. 5. dbm - decibels above or below a reference power of 1 mw into 600 ohms. 0 dbm = 0.7746 vrms. ? electrical characteristics are over recommended operating conditions, unless otherwise stated. ac electrical characteristics ? - fsk demodulation characteristics sym. min. typ. ? max. units notes* 1 accept signal level range -40 -37.78 10.0 -6.45 -4.23 476 dbv dbm mvrms 1, 2, 4, 5 2 bell 202 format reject signal level -48.24 -50.46 3 dbm dbv mvrms 1, 2, 4, 5 3 transmission rate 1188 1200 1212 baud 4 mark and space frequencies bell 202 1 (mark) bell 202 0 (space) ccitt v.23 1 (mark) ccitt v.23 0 (space) 1188 2178 1280.5 2068.5 1200 2200 1300 2100 1212 2222 1319.5 2131.5 hz hz hz hz 5 twist: 20 log (v mark /v space ) -6 +10 db 6 signal to noise ratio snr fsk 20 db 1,3 electrical characteristics ? - gain setting amplifiers characteristics sym. min. max. units test conditions 1 input leakage current i in 1 av ss v in v dd 2 input resistance r in 10 m ? 3 input offset voltage v os 25 mv 4 power supply rejection ratio psrr 30 db 1khz ripple on v dd 5 common mode rejection ratio cmrr 40 db v cmmin v in v cmmax 6 dc open loop voltage gain a vol 40 db 7 unity gain bandwidth f c 0.3 mhz 8 output voltage swing v o 0.5 v dd -0.5 v load 100k ? 9 capacitive load (gs1,gs2) c l 50 pf 10 resistive load (gs1,gs2) r l 100 k ? 11 common mode range voltage v cm 1.0 v dd -1.0 v mt88e45 data sheet 21 zarlink semiconductor inc. ? ac electrical characteristics are over recommende d operating conditions unless otherwise stated. ? ac electrical characteristics are over recommende d operating conditions unless otherwise stated. ? ac electrical characteristics are over recommende d operating conditions unless otherwise stated. ? typical figures are at 25 o c and are for design aid only: not guaranteed and not subject to production testing. *notes: 1. fsk input data at 1200 12 baud. 2. osc1 at 3.579545 mhz 0.1%. 3. function of signal condition. ac electrical characteristics ? - cas detection timing characteristics sym. min. max. units notes 1 tone present detect time t dp 0.5 10 ms see figures16 16, 1717 2 tone absent detect time t da 0.1 8 ms see figures16 16, 1717 ac electrical characteristics ? - oscillator and carrier detect timing characteristics sym. min. max. units notes 1 osc2 power-up time t pu 50 ms 2 power-down time t pd 10 ms 3 cd input fsk to cd low delay t cp 25 ms 4 input fsk to cd high delay t ca 10 ms 5hysteresis 10 ms ac electrical characteristics ? - 3-wire fsk data interface timing (mode 0) characteristics sym. min. typ. ? max. units notes* 1 dr /std rise time t rr 200 ns into 50 pf load 2fall time t rf 200 ns into 50 pf load 3low time t rl 415 416 417 s2 4 data rate 1188 1200 1212 baud 1 5 input fsk to data delay t idd 15ms 6 data dclk rise time t r 200 ns into 50 pf load 7fall time t f 200 ns into 50 pf load 8 data to dclk delay t dcd 6 416 s 1, 2, 3 9 dclk to data delay t cdd 6 416 s 1, 2, 3 10 dclk frequency f dclk0 1201.6 1202.8 1204 hz 2 11 high time t ch 415 416 417 s2 12 low time t cl 415 416 417 s2 13 dclk dr /std dclk to dr delay t crd 415 416 417 s2 mt88e45 data sheet 22 zarlink semiconductor inc. ? ac electrical characteristics are over recommende d operating conditions unless otherwise stated. figure 10 - data and dclk mode 0 output timing figure 11 - dr output timing ac electrical characteristics ? - 3-wire fsk data interface timing (mode 1) characteristics sym. min. max. units notes 1 dclk frequency f dclk1 1mhz 2 duty cycle 30 70 % 3rise time t r1 100 ns 4 dclk dr /std dclk low set up before dr t dds 500 ns 5 dclk low hold time after dr t ddh 500 ns ac electrical characteristics - timing parameter measurement voltage levels characteristics sym. level units notes 1 cmos threshold voltage v ct 0.5*v dd v 2 rise/fall threshold voltage high v hm 0.7*v dd v 3 rise/fall threshold voltage low v lm 0.3*v dd v data dclk t r t dcd t cdd t r t f t cl t ch t f v hm v lm v ct v hm v lm v ct t rf t rr t rl dr v hm v lm v ct mt88e45 data sheet 23 zarlink semiconductor inc. figure 12 - dclk mode 1 input timing figure 13 - 3-wire fsk data interface timing (mode 0) dclk t r1 v hm v lm tip/ring (a/b) wires data (output) dclk (output) dr (output) b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b6 stop start stop start stop start stop start stop start stop start t idd t crd t rl t cl t ch 1/f dclk0 mt88e45 data sheet 24 zarlink semiconductor inc. figure 14 - 3-wire fsk data interface timing (mode 1) figure 15 - application timing for bellcore on-hoo k data transmission associated with ringing, e.g., cid notes: this on-hook case application is included because a cidcw (off-hook) cpe must be also capable of receiving on-hook data transmission (with ringing) from the end office. 1) pwdn and fsken are internal signals decoded from cb0/1/2. 2) the cpe designer may choose to enable the mt88e45b only after the end of ringing to conserve power in a battery operated cpe. cd is not activated by ringing. 3) the microcontroller in the cpe powers down the mt88e45b after cd has become inactive. 4) the microcontroller times out if cd is not activated. 5) this signal represents the mode of the dr /std pin. demodulated data (internal signal) dclk (data clock) (schmitt input) dr (data ready) (output) stop start stop 0 1 234 5 67 7 word n word n+1 data (output) 5 word n word n-1 1/f dclk1 t rl >t ddh the dclk input must be low before and after dr falling edge. note 1: dclk occurs during dr low and returns dr to high. note 2: dclk occurs after dr , so dr is low for half a nominal bit time. >t dds 4 3 2 1 0 6 7 stop stop 7 0 note 1 note 2 1st ring 2nd ring ch. seizure mark data a cde f ..101010.. data note 2 note 3 note 2 note 4 t ca t cp b tip/ring pwdn osc2 fsken cd dr dclk data a = 2sec typical b = 250-500ms c = 250ms d = 150ms e = feature specific max c+d+e = 2.9 to 3.7sec f 200ms t pd t pu note 1 note 1 note 5 mt88e45 data sheet 25 zarlink semiconductor inc. figure 16 - application timing for bellcor e off-hook data transmission, e.g., cidcw notes: 1) in a cpe where ac power is not available, the designer may choose to switch over to line power when the cpe goes off-hook and use battery power while on-hook. the cpe must also be cid (on-hook) capable because a cidcw cpe includes cid functionality. 2) non-fsk signals such as cas, speech an d dtmf tones are in the same frequency band as fsk. they will be demodulated and give false data. therefore the mt88e45b should be taken out of fsk mode when fsk is not expected. 3) the mt88e45b may be put into fsk mode as soon as the cpe has finished sending the acknowledgment signal ack. tr-nwt- 000575 specifies that ack = dtmf ?d? fo r non-adsi cpe, ?a? for adsi cpe. 4) the mt88e45b should be taken out of fsk mode when cd has become inactive, or after 5 framing errors have been detected, or after 150ms of continuous mark signal or space signal has been received. the framing errors need not be consecutive. 5) in an unsuccessful attempt where the end office does not send the fsk signal, the cpe should unmute the handset and enable th e keypad after interval d has expired. 6) the total recognition time is t rec = t gp + t dp , where t gp is the tone present guard time and t dp is the tone present detect time. v tgt is the comparator threshold (refer to figure 55 for details). 7) the total tone absent time is t abs = t ga + t da , where t ga is the tone absent guard time and t da is the tone absent detect time. v tgt is the comparator threshold (refer to figure5 5 for details). 8) pwdn, hybrid casen and fsken are internal signals decoded from cb0/1/2. 9) this signal represents the mode of the dr /std pin. cpe goes off-hook cas ack cpe sends cpe mutes handset & disables keypad mark data cpe unmutes handset and enables keypad t dp t da t gp t ga t rec t abs t cp t ca data v tgt ac e f g bd note 1 note 3 note 4 note 5 tip/ring pwdn fsken osc2 est st/gt std cd dr dclk data a = 75-85 ms b = 0-100 ms c = 55-65 ms d = 0-500 ms e = 58-75 ms f = feature specific g 50 ms note 6 note 7 t pu note 8 note 8 note 9 note 2 note 9 hybrid casen note 8 mt88e45 data sheet 26 zarlink semiconductor inc. figure 17 - application timing for bt caller display service (cds), e.g., clip notes: 1) the total recognition time is t rec = t gp + t dp , where t gp is the tone present guard time and t dp is the tone present detect time. v tgt is the comparator threshold (refer to figure 55 for details). 2) the total tone absent time is t abs = t ga + t da , where t ga is the tone absent guard time and t da is the tone absent detect time. v tgt is the comparator threshold (refer to figure 55 for details). 3) by choosing t ga =15ms, t abs will be 15-25ms so that the current wetting pulse and ac load can be applied right after the std rising edge. 4) sin227 specifies that the ac and dc loads should be removed between 50-150ms after the end of the fsk signal, indicated by cd returning to high. the mt88e45b may also be powered down at this time. 5) the mt88e45b should be taken out of fsk mode when fsk is not expected to prevent the fsk demodulator from reacting to other in-band signals such as speech, dt-as/cas and dtmf tones. 6) pwdn, tip/ring casen, fsken are internal signals decoded from cb0/1/2. 7) this signal represents the mode of the dr /std pin. ch. seizure mark ..101010.. data t dp t da t gp t ga t rec t abs note 3 t cp t ca ab c d e f g zss (refer to sin227) < 0.5ma (optional) <120 a note 4 v tgt note 5 a/b wires pwdn est st/gt std te dc load te ac load fsken cd dr dclk data osc2 note 1 note 2 t pu t pd 15 1ms 20 5ms note 6 note 6 note 7 note 7 data 50-150ms note 4 tip/ring casen note 6 ring current wetting pulse (see sin227) line reversal a 100 ms b = 88-110 ms c 45 ms (up to 5sec) d = 80-262 ms e = 45-75 ms f 2.5sec (typ. 500 ms) g > 200 ms note: all values obtained from sin227 issue 1 ?idle state tone alert signal? dt-as mt88e45 data sheet 27 zarlink semiconductor inc. figure 18 - application timing for uk?s cca caller display service (cds), e.g., clip notes: 1) from tw/p&e/312. star t time: the cpe should enter the sig nalling state by applying the dc a nd ac terminations within this tim e after the end of the ring burst. 2) end time: the cpe should leave the signalling state by removing the dc and ac terminations within this time after the end of data, indicated by cd returning to high. the mt88e45b should also be taken out of fsk mode at this time to prevent the fsk demodulator from reacting to other in-band signals such as speech, and dtmf tones. 3) pwdn and fsken are internal signals decoded from cb0/1/2. 4) this signal represents the mode of the dr /std pin. ch. seizure mark data ..101010.. data note 1 t cp t ca abcdef a/b wires pwdn te dc load te ac load fsken cd dr dclk data osc2 note 2 a = 200-450 ms b 500 ms c = 80-262 ms d = 45-262 ms e 2.5s (typ. 500 ms) f >200 ms note: parameter f from "cca exceptions document issue 3" t pu t pd note 3 note 3 note 4 ring burst first complete ring cycle 250-400ms 50-150ms line reversal (optionally sent) www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. or its subsidiaries (collectively ?zarlink?) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of products are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or other intellect ual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not b een superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink?s conditi ons of sale which are available on request. purchase of zarlink?s i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in and i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright zarlink semiconductor inc. all rights reserved. technical documentation - not for resale for more information about all zarlink products visit our web site at |
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